The present invention relates to a semiconductor device and manufacturing method the semiconductor device having a MOS transistor formed on a SOI (Silicon On Insulator) substrate and capable of controlling a potential of a region, in which a channel is formed.
A substrate (an SOI substrate) having a so-called Silicon-On-Insulator (SOI) structure, in which a single crystal silicon film is formed on an insulation film, has been developed and researched from long ago because a semiconductor device having excellent performance can be realized. Since the wafer processing technique has been progressed in recent years, methods for applying the SOI substrate have energetically been investigated
FIG. 1 shows a MOS transistor having a body extended portion as an example of a conventional transistor comprising a SOI substrate and having satisfactory performance. FIGS. 2A, 2B and 2C are other conventional MOS transistors and respectively show a perspective view, a plan view and a cross sectional view taken along line 2C--2C shown in FIG. 2B.
The "body" is a portion interposed between a source and a drain (an n.sup.+ -type diffusion layer) and on which a channel of the MOS transistor will be formed. In a case of an n-channel MOS transistor, the body is a p-type silicon layer in which a low concentration p-type impurity is doped in a SOI.
The "body extended portion" is a portion which is not interposed between the source and the drain and which is a p-type silicon layer coupled to the body.
In a case of an n-channel structure, the source and the drain are n-type silicon regions in which a high concentration n-type impurity is doped in a SOI. Recently, a structure having a region, which is in contact with the channels of the source and the drain doped with low concentration n-type impurity, that is, an LDD (Lightly Doped Drain) structure, may be widely used.
An ion implantation for forming the source and the drain is performed by using a gate electrode and a resist pattern as masks after the gate electrode has been formed. A p.sup.+ -type diffusion layer is, as a contact layer, formed in a portion of the body extended portion by using the gate electrode and the resist pattern as masks.
In the structure shown in FIG. 2A, the p.sup.+ -type diffusion layer is, as shown in FIG. 2C, coupled to the gate electrode through an aluminum wiring, and then coupled to the body. The foregoing structure is also applied to the device shown in FIG. 1.
Since the potentials of the bodies of the above-mentioned MOS transistors can be controlled by adjusting the voltage which is applied to the p.sup.+ -type diffusion layer, a problem such as floating substrate effect can be suppressed when an SOI substrate is employed. Since the threshold voltage is lowered and thus a drain currents are increased if the same voltage is applied to the gate electrode and the body, a transistor which is faster than a MOS transistor formed on a bulk substrate and arranged to be operated with the same power supply voltage can be realized.
However, the MOS transistor of a type having a body extended portion has, for example, the following four problems
First Problem
Since the conventional device is structured such that the gate electrode is formed also on the body extended portion through a gate oxide film, the capacitance of the device is enlarged undesirably. Since the body extended portion is not a portion which is used as a channel portion, it is not necessary to from a capacitor having an insulation film in the form of a thin oxide film having a thickness similarly to that of the gate oxide film. That is, the capacitor is a parasitic capacitance which obstructs the high speed operation of the device.
Second Problem
The following problems arise because of a boundary (hereinafter called a "parasitic gate edge") between a source and the drain (n.sup.+ -type diffusion layer) and a body extended portion (a p-type diffusion layer) shown in FIGS. 1 and 2A.
A parasitic capacitance (a p-n junction capacitance) is, in the parasitic gate edge, formed owning to junction of the source and drain (the n.sup.+ -type diffusion layer) and the body extended portion (the p-type diffusion layer). Also the parasitic capacitance between the gate electrode and the source/drain (the gate/drain capacitance, and the gate/source capacitance) it increase. The above-mentioned parasitic capacitance inhibits the high speed performance of the device. Since leak currents increase because of the junction, disadvantage is realized when the electric power consumption is attempted to be reduced.
Third Problem
A portion of the body extended portion (the p-type diffusion layer) under the gate electrode is a silicon layer (SOI) having high resistance because substantially no impurity is introduced. As a result, the sheet resistance of the body extended portion is raised excessively to hinder the high speed operation, which is the characteristic of the device.
If the p.sup.+ -type diffusion layer is formed adjacent to the channel edge portion, the sheet resistance of the body extended portion (the p-type diffusion layer) can be reduced by a degree corresponding to the formed p.sup.+ -type diffusion layer. However, there may arise that the n-type impurity is undesirably implanted into the p.sup.+ -type diffusion layer if a mask for use when ions are implanted into the source and the drain (n.sup.+ -type diffusion layer) is deviated. Therefore, the method of reducing the body extended portion (the p-type diffusion layer) having high resistance by forming the p.sup.+ -type diffusion layer adjacent to the channel edge has a limitation.
Since the SOI substrate comprises the thin silicon layer, reduction in the resistance is an important factor. To reduce the resistance, a salicide (Self-Aligned Silicide) process is generally performed in which metal is applied by a self-alignment manner.
The salicide process has been performed such that the surface of a silicon substrate is exposed after a gate electrode has been performed. Then, metal is applied to the surface of the exposed silicon substrate. Therefore, the portion of the non-exposed body extended portion below the gate electrode cannot be formed into the salicide structure.
Fourth Problem
A fact has been known that the device shown in FIG. 2A having the body extended portion formed only adjacent to the channel edge has a difficulty in controlling the potential of the body adjacent to another channel edge as the channel width is enlarged. The foregoing problem can be overcome by controlling the potential of the body from the two sides after the body extended portions have been formed on the two sides of the channel edges.
The structure of the device shown in FIG. 2C, in which a contact hole is formed in an interlayer insulation film to couple the gate electrode and the body extended portion (the p.sup.+ -type diffusion layer) to each other through an aluminum wiring, requires a gate electrode having an opening in the central portion thereof, the size of which is similar to that of the contact hole. To prevent a problem which arises when the opening is deviated from a predetermined position, the gate electrode must be formed large. Therefore, if the body extended portion is enlarged, the area of the device is enlarged. In this case, it becomes difficult to achieve a high-integration. Moreover, the degree of freedom permitted for the contact hole and the aluminum lines is lowered by a degree corresponding to the enlargement of the body extended portion.
As described above, the conventional MOS transistor formed on a SOI substrate of a type having the body extended portion and controlling the potential of the region in which a channel will be formed has a variety of problems caused from the body extended portion.